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Department of Electrical & Computer Engineering

School of Engineering & Applied Science

Ahmed Louri

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Ahmed Louri

David and Marilyn Karlgaard Endowed Chair Professor of ECE

Contact:

Email: Ahmed Louri
Office Phone: 202-994-8241
Ahmed Louri's CV
SEH 5560 | Office hours: T: 3:30 – 4:30 pm

Dr. Ahmed Louri is the David and Marilyn Karlgaard Endowed Chair Professor of Electrical and Computer Engineering with the George Washington University, which he joined in August 2015. He is also the Director of the High Performance Computing Architectures and Technologies Laboratory. From 1988 to 2015, he was a Professor of Electrical and Computer Engineering with the University of Arizona, and during that time, he served six years (2000 to 2006) as the Chair of the Computer Engineering Program. From 2010 to 2013, Dr. Louri served as a Program Director with the National Science Foundation’s (NSF) Directorate for computer and information science and engineering.

Dr. Louri is the recipient of the IEEE Computer Society Edward J. McCluskey Technical Achievement Award (2020), IEEE Outstanding Leadership Award (2019), National Science Foundation Research Initiation Award (1989), the Best article Award from IEEE Micro, the Advanced Telecommunications Organization of Japan Fellowship, the Centre Nationale de Recherche Scientifique (CNRS), France, Fellowship, and the Japan Society for the Promotion of Science Fellowship, and several teaching awards.

Dr. Louri conducts research in the broad area of computer architecture and parallel computing, with emphasis on interconnection networks, scalable parallel computing systems, versatile and flexible computing systems, and power-efficient and reliable Network-on-Chips (NoCs) for multicore architectures. Recently, he has been concentrating on: energy-efficient, reliable, and high-performance many-core architectures; accelerator-rich reconfigurable heterogeneous architectures; secure network-on-chips for multicores and SoCs; approximate computing and communications; machine learning techniques for efficient computing, memory, and interconnect systems; heterogeneous manycore architectures and chiplet-based designs; emerging interconnect technologies (photonic, wireless, RF, hybrid) for multi-core architectures and chip multiprocessors (CMPs); future parallel computing models and architectures (including convolutional neural networks, deep neural networks, and approximate computing); and cloud-computing and data centers. He has published more than 190 refereed journal articles and peer-reviewed conference papers, and is the co-inventor on several US and international patents. His research has been sponsored by NSF, DOE, AFOSR, and a number of industrial organizations.

  • Ph.D. 1988, University of Southern California, Los Angeles, California
  • Computer Architecture
  • Scalable Multicore Architectures
  • Network-on-chips and Emerging Interconnect Technologies
  • Approximate Computing and Communications
  • Energy-Efficient Computing Systems
  • Machine-learning enabled Computing and Communication Systems
  • Secure Network-on-chips for Multicores and SoCs

Selected Publications (2016-2020):

  • Yuechen Chen, and Ahmed Louri, “A Learning-based Accuracy Management for Approximate Communication in Multi-core Systems”, in Proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Hamburg, Germany, September 20-25, 2020.
  • Quintin Fettes, Kyle Shiflett, Avinash Karanth, Razvan Bunescu and Ahmed Louri, “Hardware–based Thread Migration to Reduce On-Chip Data Movement with Reinforcement Learning,” in Proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Hamburg, Germany, September 20-25, 2020.
  • K. Wang, H. Zheng, and A. Louri, “TSA: Learning-Based Threat Detection and Mitigation for Secure System-On-Chip Architectures”, in IEEE Micro Special Issue on Machine Learning for Systems, 2020, DOI: 10.1109/MM.2020.3003576.
  • H. Zheng and A. Louri. “Agile: A Learning-enabled Power and Performance-Efficient Network-on-Chip Design,” IEEE Transactions on Emerging Topics in Computing, 2020, DOI: 10.1109/TETC.2020.3003496.
  • K. Wang and A. Louri, "CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning," in IEEE Transactions on Parallel and Distributed Systems, vol. 31, no. 9, pp. 2125-2138, 1 Sept. 2020, doi: 10.1109/TPDS.2020.2986297.
  • Kyle Shiflett, Avinash Karanth, Ahmed Louri and Razvan Bunescu, “Energy-Efficient Multiply-and-Accumulate Using Silicon Photonics for Deep Neural Networks,” in proceedings of 2020 IEEE Photonics Conference (IPC), Vancouver, Canada, 27 September - 1 October, 2020.
  • H. Zheng, K. Wang, and A. Louri, “A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures,” in proceedings of 57th Design Automation Conference (DAC’20), San Fran-cisco, July 19-23, 2020.
  • Mark Clark, Yingping Chen, Avinash Karanth, Brian Ma, and Ahmed Louri, "DoZZNoC: Reducing Static and Dynamic Energy in NoCs with Low-Latency Voltage Regulators using Machine Learning", in Proceedings of the 34th IEEE International Parallel and Distributed Processing Symposium (IPDPS), New Orleans, LA, May 18-22, 2020.
  • Y. Li, and A. Louri, "ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore Architectures", in IEEE Transactions on Sustainable Computing, DOI: 10.1109/TSUSC.2020.2981340, March 2020.
  • Y. Chen, and A. Louri, “An Approximate Communication Framework for Network-on-Chips,” in IEEE Transactions on Parallel and Distributed Systems, vol.31, issue. 6, pp. 1434 - 1446, June 2020.
  • Kyle Shiflett, Dylan Wright, Avinash Karanth, and Ahmed Louri, "PIXEL: Photonic Neural Network Accelerator", in Proceedings of the 26th IEEE International Symposium on High-Performance Computer Architecture (HPCA'20), San Diego, CA, February 22-26, 2020.
  • K. Wang, A. Louri, A. Karanth and R. Bunescu, “IntelliNoC: A Holistic Design Framework for Energy-Efficient and Reliable On-chip Communication for Manycores”, in Proceedings of the 46th International Symposium on Computer Architecture (ISCA-46), Phoenix, Arizona, June 22-26, 2019.
  • Y. Chen and A. Louri, "An Online Quality Management Framework for Approximate Communication in Network-on-Chips", in Proceedings of the 33rd International Conference on Supercomputing (ICS), Phoenix, AZ, June 26-28, 2019.
  • K. Wang, A. Louri, A. Karanth, and R. Bunescu, "High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learning", in Proceedings of the Design Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, March 25-29, 2019.
  • H. Zheng and A. Louri, “An Energy-Efficient Network-on-Chip Design using Reinforcement Learning”, in Proceedings of 56th Design Automation Conference (DAC’19), Las Vegas, NV, June 2-6, 2019.
  • T.F. Canan, S. Kaya, A. Karanth, and A. Louri, “Ultra-Compact and Low-Power Logic Circuits via Work-Function Engineering,” in IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, vol. 5, issue. 2, pp. 94-102, December 2019.
  • S. Liu, K. Chen, P. Reviriego, W. Liu, A. Louri and F. Lombardi, “Reduced Precision Redundancy for Error Tolerance and Reliable Processing of Data,” in IEEE Transactions on Emerging Topics in Computing (TETC), DOI :10.1109/TETC.2019.2947617, 2019.
  • Sikder, A. Kodi, S. Kaya, D. Carbaugh, S. Laha, A. Louri, H. Xin and J. Wu, “Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies,” in IEEE Transactions on Sustainable Computing, vol. 4, no. 3, pp. 293-307, 1 July-Sept. 2019.
  • D. Machovec, B. Khemka, N. Kumbhare, S. Pasricha, A. A. Maciejewski, H. J. Siegel, A. Akoglu, G. A. Koenig, S. Hariri, M. Wright, M. Hilton, R. Rambharos, C. Blandin, S. Hariri, C. Tunc, A. Louri and N. Imam, “Utility-Based Resource Management in an Oversubscribed Energy-Constrained Heterogeneous Environment Executing Parallel Applications,” in Parallel Computing, Vol. 83, pp. 48-72, Apr. 2019.
  • Louri, J. Collet and A. Karanth, “Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs,” in ACM Journal of Emerging Technologies for Computing, Volume 15, Issue 1, pp.4, February 2019.
  • Q. Fettes, M. Clark, R. Bunescu, A. Karanth, and A. Louri, “Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques,” in IEEE Transactions on Computers (TC), Volume 68, Issue 3, pp.375-389 , March 2019.
  • T. F. Canan, S. Kaya, A. Karanth, A. Louri, and H. Xin “Ambipolar SB-FinFETs: A New Path to Ultra-Compact sub-10nm Logic Circuits,” in IEEE Transactions on Electron Devices (TED), vol. 65, no. 12, 2018.
  • H. Zheng and A. Louri, “EZ-Pass: An Energy & Performance-Efficient Power-gating Router Architecture for Scalable NoCs,” in IEEE Computer Architecture Letters (CAL), vol. 17, no. 1, pp. 88-91, Jan. 2018.
  • J. Wu, A. K. Kodi, S. Kaya, A. Louri and H. Xin, “Monopoles Loaded With 3-D-Printed Dielectrics for Future Wireless Intrachip Communications,” in IEEE Transactions on Antennas and Propagation, vol. 65, no. 12, pp. 6838-6846, Dec. 2017.
  • T. F. Canan, S. Kaya, A. Karanth, H. Xin, and A. Louri, “10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs,” in Proceedings of the 25th International Conference on Electronic Circuits and Systems (ICECS), Bordeux, France, December 9-12, 2018.
  • Y. Chen, M.F. Reza and A. Louri, “DEC-NoC: An Approximate Framework based on Dynamic Error Control with Applications to Energy-efficient NoCs,” in Proceedings of the 36th IEEE International Conference on Computer Design (ICCD), Orlando, FL, October 7-10, 2018.
  • Y. Kelestemur, S. Laha, S. Kaya, A. Karanth, H. Xin, and A. Louri, “Sub-THz Tunable Push-Push Oscillators with FinFETs for Wireless NoCs,” in Proceedings of the 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) , Windsor, Canada, August, 5-8, 2018.
  • M. Clark, A. Kodi, R. Bunescu and A. Louri, “LEAD: Learning-enabled Energy-Aware Dynamic Voltage/Frequency Scaling in NoCs,” in Proceedings of the 55th Design Automation Conference (DAC), San Francisco, CA, June 24-28, 2018.
  • A. Kodi, K. Shiflett, S. Kaya, S. Laha and A. Louri, “Power-Efficient Kilo-Core Photonic-Wireless Hybrid NoCs,” in Proceedings of the 32nd IEEE International Symposium on Parallel and Distributed Processing (IPDPS), Vancouver, BC, May 21-25, 2018.
  • S. V. Winkle, A. Kodi, R. Bunescu and A. Louri, “Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning,” in Proceedings of the 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Vienna, February 24-28, 2018.
  • Y. Sharma, J. Wu, A. Kantemur, J. Tak, A. Kodi, S. Kaya, A. Louri and H. Xin, “Reconfigurable Intra-chip Antenna for Future Wireless Communications,” in Proceedings of the 2018 USNC-USRI National Radio Science Meeting, Boulder, CO, January 4-8, 2018.
  • P. Roychowdhury and A. Louri, “Reconfigurable All-Photonic Inter-Rack Interconnect for Data-Centers,” in Proceedings of Frontiers in Optics 2017, Washington, D.C., September 18-21, 2017.
  • T. F. Canan, S. Kaya, A. Kodi, H. Xin and A. Louri, “Ultra-compact sub-10nm logic circuits based on ambipolar SB-FinFETs,” in Proceedings of the 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, August 6-9, 2017, pp. 100-103.
  • Y. Kelestemur, S. Laha, S. Kaya, A. Kodi, H. Xin and A. Louri, “mm-Wave tunable colpitts oscillators based on FinFETs,” in Proceedings of the 2017 IEEE 18th Wireless and Microwave Technology Conference (WAMICON), Cocoa Beach, FL, April 24-25, 2017, pp. 1-6.
  • D. DiTomaso, A. Sikder, A. Kodi and A. Louri, “Machine learning enabled power-aware Network-on-Chip design,” in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, March 27-31, 2017, pp. 1354-1359.
  • D. DiTomaso, T. Boraten, A. Kodi and A. Louri, "Dynamic error mitigation in NoCs using intelligent prediction techniques," in Proceedings of the 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Taipei, October 15-19, 2016, pp. 1-12.
  • IEEE Fellow, IEEE Computer Society
  • IEEE Computer Society Edward J. McCluskey Technical Achievement Award, 2020
  • IEEE Outstanding Leadership Award, for the leadership to the field
  • Program Director, The National Science Foundation, (CCF), the Directorate for Computer & Information Science & Engineering (CISE) (2010 – 2013)
  • Invited Distinguished Professor, University of Electro-Communications (UEC), Chofu, Japan, 2010
  • Invited Distinguished Professor, Centre Nationale de la Recherche Scientifique (CNRS), Laboratoire d’Analyse et d’Architecture des Systems (LAAS), Toulouse, France, May-August 2009
  • Editor-in-Chief, IEEE transactions on Computers, January 2019- present
  • Associate Editor, IEEE Transactions on Sustainable Computing, 2015 – present
  • Associate Editor, IEEE Transactions on Cloud Computing, January 2020 – present

Recent Patents (2015 – 2020)

USPTO Full Patent filed:

  1. No. 10,148,593 “Directional Allocation of Communication Links based on Data Traffic Loads”.
  2. No. UA 08-078, “Inter-Router Dual-Function Energy and Area-Efficient Links for Network-on-Chips".
  3. No. UA 08-081 “Fault-and Variation Tolerant Energy-and Area-Efficient Links for Network-on-Chips".
  4. No.16/547,161, “EZ-Pass and Energy-Efficient and High-Performance Router Architecture for Scalable Network-on-Chips”.
  5. No. 16/547,297, “Reinforcement Learning for Fault-tolerant, Energy-efficient NoC Design”.

USPTO Provisional Patent filed:

  1. No. 63/019,720, "Learning-Based High-Performance, Energy-Efficient, and Secure Interconnection Design Framework”.
  2. No. 63/019,670, "A Versatile and Flexible Interconnection Network Design for Chiplet-Based Manycore Architecture”.
  3. No. 63/019,752, “Approximate Communication Framework for Network-on-Chips”.
  4. No. 62/853,418, “A Learning-Enabled Energy-Efficient On-Chip Interconnection".
  5. No. 62/853,455, "A Machine Learning-Based, High-Performance, Energy-Efficient, and Reliable Network-on-Chip Design”.

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