Maximizing Potential

July 14, 2017

Think of him as the brains behind “the brains.” Guru Venkataramani of the Department of Electrical and Computer Engineering studies computer architecture, unceasingly searching for ways to improve the performance, power, and security of computer processors, which he describes as the “brains behind computing systems.”

“My area is a very practical field,” he says. “We’re involved in the design of processors that go into everything from cell phones, to laptops, to super computers, to data centers.”

Dr. Venkataramani finds no shortage of interesting challenges in his field. One area in which he’s been particularly successful is performance debugging in multi-core processors, or finding the bottlenecks in an application in order to take full advantage of a processor’s resources and maximize its speed and performance.

“The question I’m trying to answer is, ‘Am I maximizing the potential and taking full advantage of the resources I have, or if not, where is the gap in my application?’ I want my four-core processor to run four times as fast as a one-core processor,” he declares.

Dr. Venkataramani explains that a number of hardware features usually are insufficiently utilized by software applications that run on top of them. This eventually contributes to the performance gap, but programmers who don’t understand what is happening inside the processor’s cores often won’t be able to figure out what the problem is. So he is developing an integrated hardware-software approach to overcome the bottlenecks in performance when more cores are added to a system. His approach shows enough promise that the National Science Foundation selected him to receive a 2012 Faculty Early CAREER Award, the most prestigious grant it awards to junior faculty.

On the security side, Dr. Venkataramani is developing a novel approach to hardware covert timing channel detection. Traditionally, researchers look at the problem in the context of networks or software structures, but Dr. Venkataramani’s group explores the problem from the hardware dimension.

“Our approach was the first in the field to address the detection of covert timing channels that can be prevented on shared hardware,” he says. “The proof that it’s exciting and novel work is that it was published in the MICRO conference, one of the top two conferences in our field. Many of the papers that are published in this conference eventually become features in real-world processors, and our work already is generating some interest.”

Last year, he also started working on a new challenge in collaboration with his colleague, Dr. Tian Lan. Their project, sponsored by the Office of Naval Research, aims to detect sensitive information leakage in user programs. The detection techniques that others have found involve a trade-off between speed and preciseness, but Dr. Venkataramani is hoping to find a synergistic approach that meets both requirements.